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a8351601 series bar code reader (july, 2002, version 1.0 ) amic technology, inc. document title bar code reader revision history rev. no. history issue date remark 0.0 initial issue june 5, 2000 preliminary 0.1 change document title from ?bar code reader? to june 22, 2000 ?8 bit microcontroller? error correction: (1) delete single - step operation description (2) delete ?the only exit from power down is a hardware reset? on page 32 0.2 modify 44l qfp package outline drawing and dimensions november 15, 2000 0.3 modify pwm function january 17, 2001 (1) add pwm3 delay control bits d0, d1 and d2 (2) add pwm4 output control bit pwm1.7 0.4 error correction: june 6, 2001 delete functional description 0.5 change document title from ?8 bit microcontroller? to october 16, 2001 ?bar code read er? 0.6 modify ac, dc electrical characteristics: february 19, 2002 add 3v 10% condition 1.0 sfr map address has some typewriting errors july 12, 2002 final modify dc and ac electrical characteristics final version release
a8351601 series bar code reader (july , 2002, version 1.0 ) 1 amic technology, inc. features n 80c32 cpu core n build in 64k byte otp rom n build in 8k byte external sram (0000h - 1fffh), c an be disable by sfr n fully pin compatible with standard 8051 family interface n instruction set compatible with 8051 family n option frequency 4.5v - 5.5v:0 - 40mhz, 2.7v - 3.3v:0 - 16mhz n power saving operation: idle is compatible with 8051 family power down can be wake up by external interrupt n port0~port3 with internal pull - up n four channel pwm output for plcc & qfp package n capture function with t2ex reversed mode n operation temperature: - 10 c~70 c n esd > 3kv n double frequency selected by sfr general description t he amic a8351601 is a high - performance 8 - bit microcontroller. it is compatible with the industry standard 80c52 microcontroller series. the a8351601 contains a on chip 256 byte ram, 64k byte otp rom, 8k byte external data sram, four 8 - bit bidirectional par allel ports, three 16 - bit timer/counters, a serial port and six interrupt sources with two priority levels. the a8351601 has supports 64kb external data memory.
a8351601 series (july, 2002, version 1.0 ) 2 amic technology, inc. t2,p1.0 t2ex,p1.1 p1.2 txd,p3.1 xtal2 xtal1 gnd p0.2,ad2 p0.1,ad1 p0.0,ad0 vcc a8351601 21 p0.3,ad3 p1.3 p1.4 p1.6 p1.7 rst rxd,p3.0 t1,p3.5 int0,p3.2 p1.5 psen ale ea p0.7,ad7 p0.6,ad6 p0.5,ad5 p0.4,ad4 20 19 18 12 16 17 13 14 15 11 10 9 8 7 6 5 4 3 2 1 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 a8351601l p1.5 p1.4 int1,p3.3 t0,p3.4 wr,p3.6 rd,p3.7 p2.7,a15 p2.6,a14 p2.5,a13 p2.4,a12 p2.3,a11 p2.2,a10 p2.1,a9 p2.0,a8 p1.3 p1.2 p1.1,t2ex p1.0,t2 pwm1 vcc p0.0,ad0 p0.1,ad1 p0.2,ad2 p0.3,ad3 p1.6 p1.7 rst rxd,p3.0 pwm2 txd,p3.1 int0, p3.2 int1,p3.3 t0,p3.4 t1,p3.5 p0.4,ad4 ea pwm4 ale psen p2.7,a15 p2.6,a14 p2.5,a13 28 27 26 25 24 23 22 21 20 19 18 44 43 42 41 40 1 2 3 4 5 6 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 p0.5,ad5 p0.6,ad6 p0.7,ad7 wr,p3.6 rd,p3.7 xtal2 xtal1 gnd pwm3 p2.0,a8 p2.1,a9 p2.2,a10 p2.3,a11 p2.4,a12 pin configurations n p - dip n plcc n qfp a8351601f p1.5 p1.4 p1.3 p1.2 p1.1,t2ex p1.0,t2 pwm1 vcc p0.0,ad0 p0.1,ad1 p0.2,ad2 p0.3,ad3 p1.6 p1.7 rst rxd,p3.0 pwm2 txd,p3.1 int0, p3.2 int1,p3.3 t0,p3.4 t1,p3.5 p0.4,ad4 ea pwm4 ale psen p2.7,a15 p2.6,a14 p2.5,a13 22 21 20 19 18 17 16 15 14 13 12 38 37 36 35 34 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 p0.5,ad5 p0.6,ad6 p0.7,ad7 wr,p3.6 rd,p3.7 xtal2 xtal1 gnd pwm3 p2.0,a8 p2.1,a9 p2.2,a10 p2.3,a11 p2.4,a12
a8351601 series (july, 2002, version 1.0 ) 3 amic technology, inc. block diagr am cpu core timing and control psen ale ea rst oscillator xtal1 xtal2 port 0 p0.0-p0.7 address (ad0-ad7) port 2 p2.0-p2.7 address a8-a15 port 1 timer 2 interrupt serial port timer 0.1 port 3 p1.0-p1.7 p3.0-p3.7 256b ram pwm sfr 64kb otp 8kb sram
a8351601 series (july, 2002, version 1.0 ) 4 amic technology, inc. pin description pin no. symbol p - dip plcc qfp i/o description ale 30 33 27 o address latch enable: output pulse for latching the low byte of the address during an address to the external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ea 31 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh. if ea is held high, the device executes from internal program memory. p0.0 - p0.7 32 - 39 36 - 43 30 - 37 i/o port 0: p ort 0 is an 8 - bit bidirectional i/o port with internal pullups. port 0 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. port 0 is also the multiplexed low - order address and data bus during accesses to ext ernal program and data memory. 1 - 8 2 - 9 40 - 44 i/o port 1: port 1 is an 8 - bit bidirectional i/o port with internal pullups. port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). the port 1 output buffers can sink/source four ttl inputs. 1 2 40 i t2 (p1.0): timer/counter 2 external count input. p1.0 - p1.7 2 3 41 i t2e x (p1.1): timer/counter 2 trigger input. p2.0 - p2.7 21 - 28 24 - 31 18 - 25 i/o port 2: port 2 is an 8 - bit bidirectional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. a s inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). port 2 emits the high order address byte during fetches from external program memory and during accesses to external da ta memory that used 16 - bit addresses (movx @ dptr). in this application, port 2 uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8 - bit addresses (movx @ ri [i = 0, 1]), port 2 emits the contents of the p2 spec ial function register. port 2 also receives the high - order bits and some control signals during rom verification.
a8351601 series (july, 2002, version 1.0 ) 5 amic technology, inc. pin description (continued) pin no. symbol p - dip plcc qfp i/o description p3.0 - p3.7 10 - 17 11,13 - 19 5, 7 - 13 i/o port 3: port 3 is an 8 - bit bidirectional i/o port with internal pullups. port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). port 3 also serves the special features of the a8351601, as listed below: 10 11 5 i rxd (p3.0): serial input port. 11 13 7 o txd (p3.1): serial output port. 12 14 8 i int0 (p3.2): external in terrupt 0. 13 15 9 i int1 (p3.3): external interrupt 1. 14 16 10 i t0 (p3.4): timer 0 external input. 15 17 11 i t1 (p3.5): timer 1 external input. 16 18 12 o wr (p3.6): external data memory write strobe. 1 7 19 13 o rd (p3.7): external data memory read strobe. psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle except that two psen actives are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. pwm1 1 39 o pulse width modulation 1 output. pwm2 12 6 o pulse width modulation 2 output. pwm3 23 17 o (d2, d1, d0) controlled the delay tim e of pwm3 from 4 clk to 11 clk after pwm1 change. pwm4 34 28 o pwm1.7: 1 is pwm3/4096, 75% duty (3072 pwm3 cycle high, 1024 pwm3 cycle low) pwm1.7: 0 is pwm3/1024, 67% duty (2048 pwm3 cycle high, 1024 pwm3 cycle low) xtal1 19 21 15 i crystal 1: input to the inverting oscillator and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator. gnd 20 22 16 i ground: 0v reference. vcc 40 44 38 i power supply: this is the power supply voltage for operat ion.
a8351601 series (july, 2002, version 1.0 ) 6 amic technology, inc. operating description the detail description of the a8351601 included in this description are: n memory map and registers n timer/counters n serial interface n interrupt system n other information memory map and registers memory the a8351601 has separate ad dress spaces for program and data memory. the program and data memory can be up to 64k bytes. the a8351601 has 256 bytes of on - chip ram, plus numbers of special function registers. the lower 128 bytes can be accessed either by direct addressing or by indi rect addressing. the upper 128 bytes can be accessed by indirect addressing only. figure 1 shows internal data memory organization and sfr memory map. the lower 128 bytes of ram can be divided into three segments as listed below. 1. register banks 0 - 3: loc ations 00h through 1fh (32 bytes). the device after reset defaults to register bank 0. to use the other register banks, the user must select them in software. each register bank contains eight 1 - byte registers r0 - r7. reset initializes the stack point to lo cation 07h, and is incremented once to start from 08h, which is the first register of the second register bank. 2. bit addressable area: 16 bytes have been assigned for this segment 20h - 2fh. each one of the 128 bits of this segment can be directly addresse d (0 - 7fh). each of the 16 bytes in this segment can also be addressed as a byte. 3. scratch pad area: 30h - 7fh are available to the user as data ram. however, if the data pointer has been initialized to this area, enough bytes should be left aside to preven t sp data destruction. special function registers the special function registers (sfr's) are located in upper 128 bytes direct addressing area. the sfr memory map in figure 1 shows that. f8 ff f0 b f7 e8 ef e0 acc e7 d8 df d0 psw rcap2l rcap2h tl2 th2 d7 c8 t2con cf c0 c7 b8 ip bf b0 p3 b7 a8 ie af a0 p2 add pwm1 pwm2 a7 98 scon sbuf 9f 90 p1 97 88 tcon tmod tl0 tl1 th0 th1 8f 80 p0 sp dpl dph pcon 87 bit addressable accessible by indirect addressing only accessible by direct addressing accessible by direct and indirect addressing ffh 80h ffh 80h 7fh 0 upper 128 lower 128 special function registers ports, status and control bits, timer, registers, stack pointer, accumulator (etc.) figure 1. internal data memory and sfr memory map not all of the addresses are occupie d. unoccupied addresses are not implemented on the chip. read accesses to these addresses in general return random data, and write accesses have no effect. user software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. in that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1. the functions of the sfrs are outlined in the following sections. accumulator (acc) acc is the accumul ator register. the mnemonics for accumulator - specific instructions, however, refer to the accumulator simply as a. b register (b) the b register is used during multiply and divide operations. for other instructions it can be treated as another scratch pad register.
a8351601 series (july, 2002, version 1.0 ) 7 amic technology, inc. program status word (psw) . the psw register contains program status information. stack pointer (sp) the stack pointer register is eight bits wide. it is incremented before data is stored during push and call executions. while the stack may resi de anywhere in on - chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at location 08h. data pointer (dptr) the data pointer consists of a high byte (dph) and a low byte (dpl). its function is to hold a 16 - bit add ress. it may be manipulated as a 16 - bit register or as two independent 8 - bit registers. ports 0 to 3 p0, p1, p2, and p3 are the sfr latches of ports 0, 1, 2, and 3, respectively. serial data buffer (sbuf) the serial data buffer is actually two separate reg isters, a transmit buffer and a receive buffer register. when data is moved to sbuf, it goes to the transmit buffer, where it is held for serial transmission. (moving a byte to sbuf initiates the transmission.) when data is moved from sbuf, it comes from t he receive buffer. timer registers register pairs (th0, tl0), (th1, tl1), and (th2, tl2) are the 16 - bit counter registers for timer/counters 0, 1, and 2, respectively. capture registers the register pair (rcap2h, rcap2l) are the capture registers for the t imer 2 capture mode. in this mode, in response to a transition at the a8351601's t2ex pin, th2 and tl2 are copied into rcap2h and rcap2l. timer 2 also has a 16 - bit auto - reload mode, and rcap2h and rcap2l hold the reload value for this mode. control registe rs special function registers ip, ie, tmod, tcon, t2con, scon, and pcon contain control and status bits for the interrupt system, the timer/counters, and the serial port. they are described in later sections of this chapter. the detail description of each bit is as follows: psw: program status word. bit addressable. 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov - p register description: cy psw.7 carry flag. ac psw.6 auxiliary carry flag. f0 psw.5 flag 0 available to the user for general purpose. rs1 psw.4 reg ister bank selector bit 1. (1) rs0 psw.3 register bank selector bit 0. (1) ov psw.2 overflow flag. - psw.1 usable as a general purpose flag p psw.0 parity flag. set/clear by hardware each instruction cycle to indicate an odd/even number of "1" bits in the accumulator. note: 1. the value presented by rs0 and rs1 selects the corresponding register bank. rs1 rs0 register bank address 0 0 0 00h - 07h 0 1 1 08h - 0fh 1 0 2 10h - 17h 1 1 3 18h - 1fh
a8351601 series (july, 2002, version 1.0 ) 8 amic technology, inc. pcon: power control register. not bit addressable. 7 6 5 4 3 2 1 0 smod - - - gf1 gf0 pd idl register description: smod double baud rate bit. if timer 1 is used to generate baud rate and smod=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. - not implemented, reserve for future use. ( 1) - not implemented, reserve for future use. (1) - not implemented, reserve for future use. (1) gf1 general purpose flag bit. gf0 general purpose flag bit. pd power - down bit. setting this bit activates power - down operation in the a8351601. idl idle mode bit. setting this bit activates idle mode operation in the a8351601. if 1s are written to pd and idl at the same time, pd takes precedence. note: 1. user software should not write 1s to reserved bits. these bits may be used in future products to invo ke new features. ie interrupt enable register. bit addressable. 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 register description: ea ie.7 disable all interrupts. if ea=0, no interrupt will be acknowledged. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. - ie.6 not implemented, reserve for future use. (5) et2 ie.5 enables or disables timer 2 overflow interrupt. es ie.4 enable or disable the serial port interrupt. et1 ie.3 enable or disable the timer 1 overflow interrupt. ex1 ie.2 ex1 ie.2 enable or disable external interrupt 1. et0 ie.1 enable or disable the timer 0 overflow interrupt. ex0 ie.0 enable or disable external interrupt 0. note: to use any of the interrupts in the 80c51 family, t he following three steps must be taken: 1. set the ea (enable all) bit in the ie register to 1. 2. set the corresponding individual interrupt enable bit in the ie register to 1. 3. begin the interrupt service routine at the correspondi ng vector address of that interrupt (see below). interrupt source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri & ti 0023h tf2 and exf2 002bh 4. in addition, for external interrupts, pins int0 and int1 (p3.2 and p3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits it0 or it1 in the tcon register may need to be set to 0 or 1. itx = 0 level activated (x = 0, 1) itx = 1 transition activated 5. u ser software should not write 1s to reserved bits. these bits may be used in future products to invoke new features.
a8351601 series (july, 2002, version 1.0 ) 9 amic technology, inc. ip: interrupt priority register. bit addressable. 7 6 5 4 3 2 1 0 - - pt2 ps pt1 px1 pt0 px0 register description: - ip.7 not implemen ted, reserve for future use (3) - ip.6 not implemented, reserve for future use (3) pt2 ip.5 defines timer 2 interrupt priority level ps ip.4 defines serial port interrupt priority level pt1 ip.3 defines timer 1 interrupt priority level px1 ip.2 define s external interrupt 1 priority level pt0 ip.1 defines timer 0 interrupt priority level px0 ip.0 defines external interrupt 0 priority level notes: 1. in order to assign higher priority to an interrupt the corresponding bit in the ip register must be se t to 1. while an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt. 2. priority within level is only to resolve simultaneous requests of the same priority level. from high to low, interrupt sources are listed bel ow: ie0 > tf0 > ie1 > tf1 > ri or ti > tf2 or exf2 3. user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features. tcon: timer/counter control register. bit addressable. 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 register description: tf1 ip.7 timer 1 overflow flag. set by hardware when the timer/counter 1 overflows. cleared by hardware as processor vectors to the interrupt service routine. tr1 ip.6 timer 1 run control bit. set/cleared by so ftware to turn timer/counter 1 on/off. tf0 ip.5 timer 0 overflow flag. set by hardware when the timer/counter 0 overflows. cleared by hardware as processor vectors to the interrupt service routine. tr0 ip.4 timer 0 run control bit. set/cleared by softwar e to turn timer/counter 0 on/off. ie1 ip.3 external interrupt 1 edge flag. set by hardware when the external interrupt edge is detected. cleared by hardware when interrupt is processed. it1 ip.2 interrupt 1 type control bit. set/cleared by software speci fy falling edge/low level triggered external interrupt. ie0 ip.1 external interrupt 0 edge flag. set by hardware when the external interrupt edge is detected. cleared by hardware when interrupt is processed. it0 ip.0 interrupt 0 type control bit. set/cle ared by software specify falling edge/low level triggered external interrupt. tmod: timer/counter mode control register. not bit addressable. timer 1 timer 0 gate c/ t m1 m0 gate c/ t m1 m0 gate when trx (in tc on) is set and gate=1, timer/counterx will run only while intx pin is high (hardware control). when gate=0, timer/counterx will run only while trx=1 (software control). c/ t timer or counter selector. cleared for timer operation (inpu t from internal system clock). set for counter operation (input from tx input pin). m1 mode selector bit. (1) m0 mode selector bit. (1)
a8351601 series (july, 2002, version 1.0 ) 10 amic technology, inc. note 1: m1 m0 operating mode 0 0 mode 0. (13 - bit timer) 0 1 mode 1. (16 - bit timer/counter) 1 0 mode 2. (8 - bit aut o - load timer/counter) 1 1 mode 3. (splits timer 0 into tl0 and th0. tl0 is an 8 - bit timer/ counter controller by the standard timer 0 control bits. th0 is an 8 - bit timer and is controlled by timer 1 control bits.) 1 1 mode 3. (timer/counter 1 stopped). scon: serial port control register. bit addressable. 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri register description: sm0 scon.7 serial port mode specifically. (1) sm1 scon.6 serial port mode specifically. (1) sm2 scon.5 enable the multiprocessor communication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1 then ri will not be activated if the received 9 th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if valid stop bit was not received. in mode 0, sm2 should be 0. ren scon.4 set/cleared by software to enable/disable reception. tb8 scon.3 the 9th bit that will be transmitted in mode 2 and 3. set/cleared by software. rb8 scon.2 in modes 2 and 3, rb8 is the 9th data bit that was received. in mode 1, if sm2=0, rb 8 is the stop bit that was received. in mode 0, rb8 is not used. ti scon.1 transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. must be cleared by software. ri scon.0 r eceive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except see sm2). must be cleared by software. note: sm0 sm1 mode description baud rate 0 0 0 shift register fosc/12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fosc/64 or fosc/32 1 1 3 9 - bit uart variable t2con: timer/counter 2 control register. bit addressable. 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 regist er description: tf2 t2con.7 timer 2 overflow flag set by hardware and cleared by software. tf2 cannot be set when either rclk = 1 or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2 ex, and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 causes the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses fo r its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 ca uses timer 1 overflows to be used for the transmit clock.
a8351601 series (july, 2002, version 1.0 ) 11 amic technology, inc. t2con: (continued) 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 register description: exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of negative transition on t2ex if timer 2 is not being used to clock the serial port, exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 software start/stop control for timer 2. a logic 1 starts the timer. c/ t2 t2con.1 timer or counter select. 0 = internal timer. 1 = external event counter (triggered by falling edge). cp/ rl2 t2con.0 capture/reload flag. when set, captures occur on negative transitions at t2ex if exen2 =1. when cleared, auto - reloads occur either with timer 2 overflows or negative transitions at t2ex when exen2=1. when either rclk=1 or tclk=1, this bit is ignored and the timer is forced to auto - reload on timer 2 overflow. notes: timer 2 op erating modes rclk + tclk cp/ rl2 tr2 mode 0 0 1 16 - bit auto - reload 0 1 1 16 - bit capture 1 x 1 baud rate generator add(a1h): extra additional register. not bit addressable. 7 6 5 4 3 2 1 0 - - delay2 delay1 delay0 t2exrev df ramdis register description: - not implemented, reserve for future use. - not implemented, reserve for future use. d2 pwm3 delay control bit. d1 pwm3 delay control bit. d0 pwm3 delay control bit. t2exrev t2ex reverse control bit. set/cleared by software sp ecify t2ex pin reverse/no reverse. df double system frequency control bit. set/cleared by software specify xtal frequency *2 / xtal frequency. ramdis build in 8k bytes sram enable/disable control bit. set/cleared by software specify enable/disable build in 8k bytes sram. bit <5:3> 0 1 2 3 4 5 6 7 delay 4 clk 5 clk 6 clk 7 clk 8 clk 9 clk 10 clk 11 clk (d2, d1, d0) controlled the delay time of pwm3 after pwm1 change.
a8351601 series (july, 2002, version 1.0 ) 12 amic technology, inc. pwm1: pulse width modulation 1 register. not bit addressable. 7 6 5 4 3 2 1 0 - pwm1 .6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 register description: pwm1.7 pwm4 output control. set/clear by specify 75% duty/67% duty. pwm1.6 pwm1 frequency control bit. set/cleared by specify half/normal pwm1 frequency. pwm1.5 pwm1 cycle control bit. pwm1.4 pwm1 cycle control bit. pwm1.3 pwm1 cycle control bit. pwm1.2 pwm1 cycle positive edge width control bit. pwm1.1 pwm1 cycle positive edge width control bit. pwm1.0 pwm1 cycle positive edge width control bit. note: pwm1 pwm3 pwm4 delay 4~11 clk t3 3072 t3(pwm1.7:1)/2048 t3(pwm1.7:0) 1024 t3 xtal frequency = 14.7456mhz bit<5:3> 0 1 2 3 4 5 6 7 t1 1.017us 1.695us 2.373us 3.051us 3.729us 4.407us 5.085us 5.763us bit<2:0> 0 1 2 3 4 5 6 7 t2 542.4ns 67.8ns 135.6ns 203.4ns 271.2ns 339ns 406.8ns 474.6ns t2 t1
a8351601 series (july, 2002, version 1.0 ) 13 amic technology, inc. pwm2: pulse width modulation 2 register. not bit addressable. 7 6 5 4 3 2 1 0 pwm2.7 - - - pwm2.3 pwm2.2 pwm2.1 pwm2.0 register description: pwm2.7 pwm2 output control bit. set/cleared by specify enable/ground pwm2. pwm2.6 not implemented, reserve for future use. pwm2.5 not impl emented, reserve for future use. pwm2.4 not implemented, reserve for future use. pwm2.3 pwm2 frequency control bit. set/cleared by specify half/normal pwm2 frequency. pwm2.2 pwm2 cycle control bit. pwm2.1 pwm2 cycle control bit. pwm2.0 pwm2 cycle con trol bit. xtal frequency = 14.7456mhz bit<2:0> 0 1 2 3 4 5 6 7 pwm2 3600hz 2880hz 2400hz 2057hz 1600hz 1440hz 1200hz 1029hz
a8351601 series (july, 2002, version 1.0 ) 14 amic technology, inc. timer/counters the a8351601 has three 16 - bit timer/counter registers: timer 0, timer 1, and in addit ion timer 2. all three can be configured to operate either as timers or event counters. as a timer, the register is incremented every machine cycle. thus, the register counts machine cycles. since a machine cycle consists of 12 oscillator periods, the coun t rate is 1/12 of the oscillator frequency. as a counter, the register is incremented in response to a 1 - to - 0 transition at its corresponding external input pin, t0, t1, and t2. the external input is sampled during s5p2 of every machine cycle. when the sam ples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since two machine cycles (24 oscillator period s) are required to recognize a 1 - to - 0 transition, the maximum count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. in addition to the timer or counter functions, timer 0 and timer 1 have four operating modes: (13 - bit timer, 16 - bit timer, 8 - bit auto - reload, split timer). timer 2 in the a8351601 has three modes o f operation: capture, auto - reload, and baud rate generator. timer 0 and timer 1 timer/counters 0 and 1 are present in a8351601. the timer or counter function is selected by control bits c/t in the special function register tmod. these two timer/counters h ave four operating modes, which are selected by bit pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timer/ counters, but mode 3 is different. the four modes are described in the following sections. mode 0: both timers in mode 0 are 8 - bit co unters with a divide - by 32 prescaler. figure 2 shows the mode 0 operation as it applies to timer 1. in this mode, the timer register is configured as a 13 - bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf1. t he counted input is enabled to the timer when tr1= 1 and either gate= 0 or int1 = 1. setting gate= 1 allows the timer to be controlled by external input int1 , to facilitate pulse width measurements. tr1 is a control bit in the special function register tcon. gate is in tmod. the 13 - bit register consists of all eight bits of th1 and the lower five bits of tl1. the upper three bits of tl1 are indeterminate and should be ignored. setting the run flag (tr1) does not clear th e registers. mode 0 operation is the same for timer 0 as for timer 1, except that tr0, tf0 and int0 replace the corresponding timer 1 signals in figure 2. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (t mod.3). s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 s1 p1 p2 one machine cycle one machine cycle osc (xtal2) osc divide 12 c/t=0 c/t=1 t1 pin tr1 gate int1 pin control tl1 (5 bits) th1 (8 bits) tf1 interrupt figure 2. timer/counter 1 mode 0: 13-bit counter th1 (8 bits) tl1 (8 bits) tf1 overflow flag timer clock figure 3. timer/counter 1 mode 1: 16-bit counter
a8351601 series (july, 2002, version 1.0 ) 15 amic technology, inc. mode 1: mode 1 is the same as mode 0, except that the timer register is run with all 16 bits. the clock is applied to the combined high and low timer registers (tl1/th1). as clock pulses are received, the timer counts up: 0000h, 0001h, 0002h, etc . an overflow occurs on the ffffh - to - 0000h overflow flag. the timer continues to count. the overflow flag is the tf1 bit in tcon that is read or written by software (see figure 3). mode 2: mode 2 configures the timer register as an 8 - bit counter (tl1) with automatic reload, as shown in figure 4. overflow from tl1 not only sets tf1, but also reloads tl1 with the contents of th1, which is preset by software. the reload leaves the th1 unchanged. mode 2 operation is the same for timer/counter 0. mode 3: t imer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 4. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is for applications requiring an extra 8 - bit timer or coun ter. with timer 0 in mode 3, the a8351601 can appear to have four. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3. in this case, timer 1 can still be used by the serial port as a baud rate generat or or in any application not requiring an interrupt. figure 4. timer/counter 1 mode 2: 8-bit auto-reload interrupt osc divide 12 c/t=0 c/t=1 t1 pin tr1 gate int1 pin control tl1 (8 bits) tf1 th1 (8 bits) reload figure 5. timer/counter 0 mode 3: two 8-bit counters interrupt osc divide 2 c/t=0 c/t=1 t0 pin tr0 gate int0 pin control tl0 (8 bits) tf0 1/12f osc 1/12f osc interrupt th0 (8 bits) tf1 1/12f osc control tr1
a8351601 series (july, 2002, version 1.0 ) 16 amic technology, inc. timer 2 timer 2 is a 16 - bit timer/counter present only in the a8351601. this is a powerful addition to the other two just discussed. five extra special function registers are added to accommodate timer 2 which are: the timer registers, tl2 and th2, the timer control register, t2con, and the capture registers, rcap2l and rcap2h. like timers 0 and 1, it can operate either as a timer or as an event counter, depending on the value of bit c/t2 in the special function register t2con. timer 2 has three operating modes: capture, auto - reload, and baud rate generator, which are selected by rclk, tclk, cp/ rl2 and tr2. in the capture mode, the exen2 bit in t2con selects two options. if exen2=0, th en timer 2 is a 16 - bit timer or counter whose overflow sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt. if exen2=1, then timer 2 performs the same way, but a 1 - to - 0 transition at external input t2ex also causes the curren t value in the timer 2 registers, tl2 and th2, to be captured into the rcap2l and rcap2h registers, respectively. in addition, the transition at t2ex sets the exf2 bit in t2con, and exf2, like tf2, can generate an interrupt. the capture mode is illustra ted in figure 6. in the auto - reload mode, the exen2 bit in t2con also selects two options. if exen2 = 0, then when timer 2 rolls over it sets tf2 and also reloads the timer 2 registers with the 16 - bit value in the rcap2l and rcap2h registers, which are pr eset by software. if exen2 = 1, then timer 2 performs the same way, but a 1 - to - 0 transition at external input t2ex also triggers the 16 - bit reload and sets exf2. the auto - reload mode is illustrated in figure 7. the baud rate generator mode is selected by r clk = 1 and/or tclk = 1. this mode is described in conjunction with the serial port (figure 8). figure 6. timer 2 in capature mode timer 2 interrupt osc divide 12 c/t2=0 t2 pin control tl2 (8 bits) tf2 c/t2=1 th2 (8 bits) rcap2l rcap2h exf2 t2ex pin exen2 tr2 capture control transition detector
a8351601 series (july, 2002, version 1.0 ) 17 amic technology, inc. note: 1. t2ex can be used as an additional external interrupt. figure 7. timer 2 in auto-reload mode timer 2 interrupt osc divide 12 c/t2=0 t2 pin control tl2 (8 bits) tf2 c/t2=1 th2 (8 bits) rcap2l rcap2h exf2 t2ex pin exen2 tr2 reload control transition detector figure 8. timer 2 in baud rate generator mode timer 2 interrupt osc divide 12 t2 pin control tl2 (8 bits) th2 (8 bits) rcap2l rcap2h exf2 t2ex pin exen2 tr2 control transition detector reload divide 16 divide 16 rx clock tx clock "1" "1" note:osc freq. is div by 2, not 12 divide 2 "1" "0" timer 1 overflow "0" smod rclk tclk "0" c/t2=0 c/t2=1
a8351601 series (july, 2002, version 1.0 ) 18 amic technology, inc. timer set - up tables 3 through 6 give tmo d values that can be used to set up timers in different modes. it assumes that only one timer is used at a time. if timers 0 and 1 must run simultaneously in any mode, the value in tmod for timer 0 must be ored with the value shown for timer 1 (tables 5 an d 6). for example, if timer 0 must run in mode 1 gate (external control), and timer 1 must run in mode 2 counter, then the value that must be loaded into tmod is 69h (09h from table 3 ored with 60h from table 6). moreover, it is assumed that the user is n ot ready at this point to turn the timers on and will do so at another point in the program by setting bit trx (in tcon) to 1. table 3. timer/counter 0 used as a timer tmod mode timer 0 function internal control (1) external control (2) 0 13 - bit timer 00h 08h 1 16 - bit timer 01h 09h 2 8 - bit auto - reload 02h 0ah 3 two 8 - bit timers 03h 0bh table 4. timer/counter 0 used as a counter tmod mode timer 0 function internal control (1) external control (2) 0 13 - bit timer 04h 0ch 1 16 - bit timer 05h 0dh 2 8 - bit auto - reload 06h 0eh 3 one 8 - bit counter 07h 0fh notes: 1. the timer is turned on/off by setting/clearing bit tr0 in the software. table 5. timer/counter 1 used as a timer tmod mode timer 1 function internal control (1) external control (2) 0 13 - b it timer 00h 80h 1 16 - bit timer 10h 90h 2 8 - bit auto - reload 20h a0h 3 does not run 30h b0h table 6. timer/counter 1 used as a timer tmod mode timer 1 function internal control (1) external control (2) 0 13 - bit timer 40h c0h 1 16 - bit timer 50h d0h 2 8 - bit auto - reload 60h e0h 3 not available - - notes: 1. the timer is turned on/off by setting/clearing bit tr1 in the software. 2. the timer is turned on/off by the 1 to 0 transition on int1 (p3.3) when tr1 = 1 (hardware control).
a8351601 series (july, 2002, version 1.0 ) 19 amic technology, inc. ti mer/counter 2 set - up except for the baud rate generator mode, the values given for t2c0n do not include the setting of the tr2 bit. therefore, bit tr2 must be set separately to turn the timer on. table 7. timer/counter 2 used as a timer t2con mode inte rnal control (1) external control (2) 16 - bit auto - reload 00h 08h 16 - bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 8. timer/counter 2 used as a counter t2con mode internal control (1) external control (2) 16 - bit auto - reload 02h 0ah 16 - bit capture 03h 0bh notes: 1. capture/reload occurs only on timer/counter overflow. 2. capture/reload occurs on timer/counter overflow and a 1 to 0 transition on t2ex (p1.1) pin except whe n timer 2 is used in the baud rate generating mode. serial interface the serial port is full duplex, which means it can transmit and receive simultaneously. it is also receive - buffered, which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (however, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at sp ecial function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in the following four modes: mode 0: serial data enters and exits through rxd. txd outp uts the shift clock. eight data bits are transmitted/received, with the lsb first. the baud rate is fixed at 1/12 the oscillator frequency (see figure 9). mode 1: ten bits are transmitted (through txd) or received (through rxd): a start bit (0), eight data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable (see figure 10). mode 2: eleven bits are transmitted (through txd) or received (through rxd): a start bit (0), eight data bits (lsb first), a programmable ninth data bit, and a stop bit (1). on transmit, the ninth data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) can be moved into tb8. on receive, the ninth data b it goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency (see figure 11). mode 3: eleven bits are transmitted (through txd) or received (through rxd): a start bit (0), eight data bits (lsb first), a programmable ninth data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except the baud rate, which is variable in mode 3 (see figure 12). in all four modes, transmission is init iated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1.
a8351601 series (july, 2002, version 1.0 ) 20 amic technology, inc. oscillator frequency 12 x [256 - (th1)] multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, nine data bits are received, followed by a stop bit. the ninth bit goes into rb8; then comes a stop bit. the port can be programmed such that when the stop bit is received, t he serial port interrupt is activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. the following example shows how to use the serial interrupt for multiprocessor communications. when the master processor must transmit a block of da ta to one of several slaves, it first sends out an address byte that identifies the target slave. an address byte differs from a data byte in that the ninth bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave is interrupted by a data b yte. an address byte, however, interrupts all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave clears its sm2 bit and prepares to receive the data bytes that follows. the slaves that are not add ressed set their sm2 bits and ignore the data bytes. sm2 has no effect in mode 0 but can be used to check the validity of the stop bit in mode 1. in a mode 1 reception, if sm2 = 1, the receive interrupt is not activated unless a valid stop bit is received. baud rates the baud rate in mode 0 is fixed as shown in the following equation. mode 0 baud rate = 12 frequency oscillator the baud rate in mode 2 depends on the value of the smod bit in special function register pcon. if smod= 0 (the value on reset), the baud rate is 1/64 of the oscillator frequency. if smod = 1, the baud rate is 1/32 of the oscillator frequency, as shown in the following equation. mode 2 baud rate = 64 2 smod x (oscillator frequency) in the a8351601, the baud rates can be d etermined by timer 1, timer 2, or both (one for transmit and the other for receive). using the timer 1 to generate baud rates when timer 1 is the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the valu e of smod according to the following equation. mode 1,3 baud rate = 32 2 smod x (timer 1 overflow rate) the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operation in a ny of its 3 running modes. in the most typical applications, it is configured for timer operation in auto - reload mode (high nibble of tmod =0010b). in this case, the baud rate is given by the following formula. mode 1,3 baud rate = 32 2 smod x programmers can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16 - bit timer (high nibble of tmod =0001b), and using the timer 1 interrupt to do a 16 - bit software reload. table 9 list s commonly used baud rates and how they can be obtained from timer 1.
a8351601 series (july, 2002, version 1.0 ) 21 amic technology, inc. modes 1,3 baud rate using timer 2 to generate baud rates in the a8351601, setting tclk and/or rclk in t2con selects timer 2 as the baud rate generator. under these conditions, the baud rates for transmit a nd receive can be simultaneously different. setting rclk and/or tclk puts timer 2 into its baud rate generator mode, as shown in figure 8. the baud rate generator mode is similar to the auto - reload mode, in that a rollover in th2 reloads the timer 2 regist ers with the 16 - bit value in the rcap2h and rcap2l registers, which are preset by software. in this case, the baud rates in mode 1 and 3 are determined by the timer 2 overflow rate according to the following equation. modes 1,3 baud rate = 16 rate overflow 2 timer timer 2 can be configured for either timer or counter operation. in the most typical applications, it is configured for timer operation (c/ t2 = 0). normally, a timer increments every machine cycle (thus at 1/12 the oscillator f requency), but timer operation is a different for timer 2 when it is used as a baud rate generator. as a baud rate generator, timer 2 increments every state time (thus at 1/2 the oscillator frequency). in this case, the baud rate is given by the following formula. = rcap2l)] (rcap2h, - [65536 x 32 frequency oscillator table 9. commonly used baud rates generated by timer 1 where (rcap2h, rcap2l) is the content of rcap2h and rcap2l taken as a 16 - bit unsigned integer. figure 7 shows timer 2 as a baud rate gener ator. this figure is valid only if rclk + tclk = 1 in t2con. a rollover in th2 does not set tf2 and does no generate an interrupt. therefore, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. if exen2 is se t, a 1 - to - 0 transition in t2ex sets exf2 but does not cause a reload from (rcap2h, rcap2l) to (th2, tl2). thus, when timer 2 is used as a baud rate generator, t2ex can be used as an extra external interrupt. when timer 2 is running (tr2 = 1) as a timer in the baud rate generator mode, programmers should not read from or write to th2 or tl2. under these conditions, timer 2 is incremented every state time, and the results of a read or write may not be accurate. the rcap registers may be read, but should not b e written to, because a write might overlap a reload and cause write and/or reload errors. turn timer 2 off (clear tr2) before accessing the timer 2 or rcap registers, in this case. timer 1 baud rate f osc smod c/ t mo de reload value mode 0 max: 1 mhz 12 mhz x x x x mode 2 max: 375k 12 mhz 1 x x x modes 1,3: 62.5k 12 mhz 1 0 2 ffh 19.2k 11.059 mhz 1 0 2 fdh 9.6k 11.059 mhz 0 0 2 fdh 4.8k 11.059 mhz 0 0 2 fah 2.4k 11.059 mhz 0 0 2 f4h 1.2k 11.059 mhz 0 0 2 e8h 1 37.5 11.986 mhz 0 0 2 1dh 110 6 mhz 0 0 2 72h 110 12 mhz 0 0 1 feebh
a8351601 series (july, 2002, version 1.0 ) 22 amic technology, inc. more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted/received, with the lsb first. the baud rate is fixed at 1/12 the oscillator frequency. figure 9 shows a simplified functional diagram of the serial port in mode 0 and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the "write to sbuf" signal at s6p2 also load s a 1 into the ninth position of the transmit shift register and tells the tx control block to begin a transmission. the internal timing is such that one full machine cycle will elapse between "write to sbuf" and activation of send. send transfer the outpu t of the shift register to the alternate output function line of p3.0, and also transfers shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift register are shifted one position to the right. as data bits shift out to the right, 0s come in from the left. when the msb of the data byte is at the output position of the s hift register, the 1 that was initially loaded into the ninth position is just to the left of the msb, and all positions to the left of that contain 0s. this condition flags the tx control block to do one last shift, then deactivate send and set ti. both o f these actions occur at s1p1 of the tenth machine cycle after "write to sbuf." reception is initiated by the condition ren = 1 and ri = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register and ac tivates receive in the next clock phase. receive enables shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the conten ts of the receive shift register are shifted on position to the left. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. whe n the 0 that was initially loaded into the right - most position arrives at the left - most position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared and ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), eight data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the a8351601 t he baud rate is determined either by the timer 1 overflow rate, the timer 2 overflow rate, or both. in this case, one timer is for transmit, and the other is for receive. figure 10 shows a simplified functional diagram of the serial port in mode 1 and asso ciated timings for transmit and receive. transmission is initiated by any instruction that uses sbuf as a destination register. the "write to =sbuf" signal also loads a 1 into the ninth bit position of the transmit shift register and flags the tx control u nit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide - by - 16 counter. thus, the bit times are synchronized to the divide - by - 16 counter, not to the "write to sbuf" signal. the transmission begins when send is activated, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, 0s are clocked in from the left. when the msb of the data byte is at the output position of the shift register, the 1 that was initially loaded into the ninth position is just to the left of the msb, and all positions to the left of that contain 0s. this condition flags the tx control unit to do one last shift, then deactivate send and set ti. this occurs at the tenth divide - by - 16 rollover after "write to sbuf". reception is initiated by a 1 - to - 0 transition detected at rxd. for this purpose, rxd is sampled at a rate of 16 times the established baud rate. when a transition is detected, the divide - by - 16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide - by - 16 counter aligns its rollover s with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16th. at the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least two of the three samples. this is done to reject noise. in order to reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1 - to - 0 transiti on. if the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds.
a8351601 series (july, 2002, version 1.0 ) 23 amic technology, inc. as data bits come in from the right, 1s shift to the left. when the start bit arrives at the leftmost position in the shift regist er, (which is a 9 - bit register in mode 1), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8 and to set ri is generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. ri = 0 and 2. either sm2 = 0, or the received stop bit =1 if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the eight data bits go i nto sbuf, and ri is activated. at this time, whether or not the above conditions are met, the unit continues looking for a 1 - to - 0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable ninth data bit, and a stop bit (1). on transmit, the ninth data bit (tb8) can be assigned the value of 0 or 1. on receive, the ninth data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 o r 1/64 of the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from either timer 1 or 2, depending on the state of tclk and rclk. figures 11 and 12 show a functional diagram of the serial port in modes 2 and 3. the receive por tion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the ninth bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the "write to sbuf" signal also loa ds tb8 into the ninth bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide - by - 16 counter. thus, the bit tim es are synchronized to the divide - by - 16 counter, not to the "write to sbuf" signal. the transmission begins when send is activated, which puts the start bit at txd. one bit timer later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the ninth bit position of the shift register. thereafter, only 0s are clocked in. thus, as data bits shift out to the right, 0s are clocke d in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain 0s. this condition flags the tx control unit to do one last shift, then deactivate sen d and set ti. this occurs at the 11th divide - by - 16 rollover after "write to sbuf". reception is initiated by a 1 - to - 0 transition detected at rxd. for this purpose, rxd is sampled at a rate of 16 times the established baud rate. when a transition is detec ted, the divide - by - 16 counter is immediately reset, and 1ffh is written to the input shift register. at the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least two of the three samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1 - to - 0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. as data bits come in from the right, is shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9 - bit register), it flags the r x control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8 and to set ri is generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. ri = 0, and 2. either sm2 = 0 or the received 9th data bit = 1 if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received ninth data bit goes into rb8, and the first eight data bits go into sbuf. on e bit time later, whether the above conditions were met or not, the unit continues looking for a 1 - to - 0 transition at the rxd input. note that the value of the received stop bit is irrelevant to sbuf, rb8, or ri. table 10. serial port setup mode scon sm 2variation 0 10h 1 50h 2 90h 3 d0h single processor environment (sm2=0) 0 na 1 70h 2 b0h 3 f0h multiprocessor environment (sm2=1)
a8351601 series (july, 2002, version 1.0 ) 24 amic technology, inc. serial port mode 0 sbuf zero detector s q d cl tx contorl shift send start tx clock shift rx contorl receive shift rx clock start ri input shift reg. 1 1 1 1 1 1 1 0 shift clock rxd p3.0 alt output function txd p3.1 alt output function serial port interrupt write to sbuf s6 ren ri shift rxd p3.0 alt input function sbuf a8351601 internal bus load sbuf read sbuf s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ri receive rxd ( d in ) txd ( s hift clock) write to scon (clear ri) d2 d1 d3 d4 d5 d6 d0 d7 transmit ale send shift rxd ( d out ) txd ( s hift clock) ti write to sbuf s6p2 s3p1 s6p1 receive shift s5p2 figure 9. serial port mode 0
a8351601 series (july, 2002, version 1.0 ) 25 amic technology, inc. serial port mode 1 sbuf zero detector s q d cl tx contorl data send start rx clock rx contorl load sbuf shift rx clock start ri input shift reg. (9sbits) 1ffh txd serial port interrupt write to sbuf shift sbuf a8351601 internal bus load sbuf read sbuf figure 10. serial port mode 1 transmit s1p1 start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit tx clock write to sbuf send data shift txd ti rx clock reset 16 ? rxd bit detector sample times receive shift ri stop bit start bit d0 d1 d2 d3 d4 d5 d6 d7 a8351601 internal bus tb8 shift ti 16 ? 1-to-0 transition detector sample bit detector rxd timer2 overflow 16 ? 2 ? rclk tclk smod =0 smod =1 timer1 overflow "0" "1" "1" "0"
a8351601 series (july, 2002, version 1.0 ) 26 amic technology, inc. serial port mode 2 sbuf zero detector s q d cl tx contorl data send start tx clock rx contorl load sbuf shift rx clock start ri input shift reg. (9 bits) 1ffh txd serial port interrupt write to sbuf shift sbuf a8351601 internal bus load sbuf read sbuf figure 11. serial port mode 2 transmit s1p1 start bit d0 d1 d2 d3 d4 d5 d6 tb8 stop bit write to sbuf data shift txd ti rx clock reset 16 ? rxd bit detector sample times receive shift ri stop bit start bit d0 d1 d2 d3 d4 d5 d6 rb8 a8351601 internal bus tb8 shift ti 16 ? 1-to-0 transition detector sample bit detector rxd 16 ? 2 ? stop bit gen smod1 smod0 phase 2 clock (1/2 fosc) mode 2 (smod is pcon.7) tx clock send stop bit gen d7 d7
a8351601 series (july, 2002, version 1.0 ) 27 amic technology, inc. serial port mode 3 sbuf zero detector s q d cl tx contorl data send start rx clock rx contorl load sbuf shift rx clock start ri input shift reg. (9 bits) 1ffh txd serial port interrupt write to sbuf shift sbuf a8351601 internal bus load sbuf read sbuf a8351601 internal bus tb8 shift ti 16 ? 1-to-0 transition detector sample bit detector rxd timer2 overflow 16 ? 2 ? rclk tclk smod =0 smod =1 timer1 overflow "0" "1" "1" "0" figure 12. serial port mode 3 transmit s1p1 start bit d0 d1 d2 d3 d4 d5 d6 stop bit write to sbuf data shift txd ti tx clock send stop bit gen d7 tb8 rx clock reset 16 ? rxd bit detector sample times receive shift ri stop bit start bit d0 d1 d2 d3 d4 d5 d6 rb8 d7
a8351601 series (july, 2002, version 1.0 ) 28 amic technology, inc. interrupt system the a8351601 provides six interrupt sources: two external interrupts, three timer interrupts, and a serial port interrupt. these are shown in figure 13. the external interr upts int0 and int1 can each be either level - activated or transition - activated, depending on bits it0 and it1 in register tcon. the flags that actually generate these interrupts are the ie0 and ie1 bits in tcon. whe n the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was transition - activated. if the interrupt was level - activated, then the external requesting source (rather than the on - chip hardware) controls the request flag. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers (except for timer 0 in mode 3). when a timer interrupt is generated, the on - chip hardware c lears the flag that generated it when the service routine is vectored to. the serial port interrupt is generated by the logical or of ri and ti. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine normally must determine whether ri or ti generated the interrupt, and the bit must be cleared in software. in the a8351601, the timer 2 interrupt is generated by the logical or of tf2 and exf2. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine may have to determine whether tf2 or exf2 generated the interrupt, and the bit must be cleared in software. all of the bits that generate interrupts can be set or cleared by software, with the s ame result as though they had been set or cleared by hardware. that is, interrupts can be generated and pending interrupts can be canceled in software. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function register ie (interrupt enable) at address 0a8h. as well as individual enable bits for each interrupt source, there is a global enable/disable bit that is cleared to disable all interrupts or set to turn on interrupts (see sfr ie). external int rqst 0 tcon.1 ie0 timer/counter 0 tcon.5 tf0 external int rqst 1 tcon.3 ie1 timer/counter 1 tcon.7 tf1 internal serial port scon.0 ri scon.1 ti timer/ counte2 t2con.7 tf2 t2con.6 exf2 int0 int1 t2ex ie.0 ex0 ie.1 et0 ie.2 ex1 ie.3 et1 ie.4 es ie.5 et2 ie.7 ea ip.0 px0 ip.1 pt0 ip.2 px1 ip.3 pt1 ip.4 ps ip.5 pt2 source i.d. source i.d. polling hardware high priority interrupt request vector low priority interrupt request vector figure 13. interrupt system
a8351601 series (july, 2002, version 1.0 ) 29 amic technology, inc. priorit y level structure each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in special function register ip (interrupt priority) at address 0b8h. ip is cleared after a system reset to place all int errupts at the lower priority level by default. a low - priority interrupt can be interrupted by a high - priority interrupt but not by another low - priority interrupt. a high - priority interrupt can not be interrupted by any other interrupt source. if two reque sts of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus, wit hin each priority level there is a second priority structure determined by the polling sequence, as follows: source priority within level 1. ie0 (highest) 2. tf0 3. ie1 4. tf1 5. ri + ti 6. tf2 + exf2 (lowest) note that the "priority within lev el" structure is only used to resolve simultaneous requests of the same priority level. how interrupts are handled the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle (the timer 2 inte rrupt cycle is different, as described in the response timer section). if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service rou tine, provided this hardware generated lcall is not blocked by any of the following conditions: 1. an interrupt of equal or higher priority level is already in progress. 2. the current (polling) cycle is not the final cycle in the execution of the instruct ion in progress. 3. the instruction in progress is reti or any write to the ie or ip registers. any of these three conditions will block the generation of the lcall to the interrupt service routine. condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. condition 3 ensures that if the instruction in progress is reti or any access to ie or ip, then at least one more instruction will be executed before any interrupt is vectored to. the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the previous machine cycle. if an active interrupt flag is not being serviced because of one of the above conditions and is not still active when the blocki ng condition is removed, the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. the polling cycle/lcall sequence is illustrated in figure 1 4. note that if an interrupt of higher priority level goes active prior to s5p2 of the machine cycle labeled c3 in figure 14, then in accordance with the above rules it will be serviced during c5 and c6, without any instruction of the lower priority routin e having been executed. ~ ~ ~ ~ ~ ~ c2 c3 c4 c5 c1 s5p2 interrupt goes active interrupt latched interrupts are polled long call to interrupt vector address interrupt routine s6 e figure 14. interrupt response timing diagram
a8351601 series (july, 2002, version 1.0 ) 30 amic technology, inc. thus, the processor acknowledges an interrupt request by executing a hardware - generated lcall to the appropriate servicing routine. in some cases it also clears the flag that generated the interrupt, and in other cases it does not. it never clears the serial port or timer 2 flags. this must be done in the user's software. the processor clears an external interrupt flag (ie0 or ie1) only if it was transition - activated. the hardware - generated lcall pushes the contents of the program c ounter onto the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being serviced, as follows: interrupt source interrupt request bits cleared by hardware vector address int0 ie0 no (level) yes (trans.) 0003h timer 0 tf0 yes 000bh int1 ie1 no (level) yes (trans.) 0013h timer 1 tf1 yes 001bh serial port ri, ti no 0023h timer 2 tf2, exf2 no 002bh system reset rst 0000h execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted p rogram continues from where it left off. note that a simple ret instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. interrupt flag sfr register and bit position external 0 ie0 tcon.1 external 1 ie1 tcon.3 timer 1 tf1 tcon.7 timer 0 tf0 tcon.5 serial port ti scon.1 serial port tf2 ri t2con.7 scon.0 timer 2 timer 2 exf2 t2con.6 when an interrupt is accepted the following action o ccurs: 1. the current instruction completes operation. 2. the pc is saved on the stack. 3. the current interrupt status is saved internally. 4. interrupts are blocked at the level of the interrupts. 5. the pc is loaded with the vector address of the isr (i nterrupts service routine). 6. the isr executes. the isr executes and takes action in response to the interrupt. the isr finishes with reti (return from interrupt) instruction. this retrieves the old value of the pc from the stack and restores the old inte rrupt status. execution of the main program continues where it left off. external interrupts the external sources can be programmed to be level - activated or transition - activated by setting or clearing bit it1 or it0 in register tcon. if itx= 0, external in terrupt x is triggered by a detected low at the intx pin. if itx = 1, external interrupt x is edge - triggered. in this mode if successive samples of the intx pin show a high in one cycle and a low in the next cycle, interrupt request flag iex in tcon is set . flag bit iex then requests the interrupt. since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. if the external interrupt is transition - activated, th e external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag iex will be set. iex will be automatically cleared b y the cpu when the service routine is called. if the external interrupt is level - activated, the external source has to hold the request active until the requested interrupt is actually generated. then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. response time the int0 and int1 levels are inverted and latched into the interrupt flags ie0 and ie1 at s5p2 of every machine cycle. similarly, the timer 2 flag exf2 and the serial port flags ri and ti are set at s5p2. the values are not actually polled by the circuitry until the next machine cycle. the timer 0 and timer 1 flags, tf0 and tf1, are set at s5p2 of the cycle in whic h the timers overflow. the values are then polled by the circuitry in the next cycle. however, the timer 2 flag tf2 is set at s2p2 and is polled in the same cycle in which the timer overflows.
a8351601 series (july, 2002, version 1.0 ) 31 amic technology, inc. if a request is active and conditions are right for it to be a cknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. the call itself takes two cycles. thus, a minimum of three complete machine cycles elapsed between activation of an external interrupt request a nd the beginning of execution of the first instruction of the service routine. figure 13 shows response timings. a longer response time results if the request is blocked by one of the three previously listed conditions. if an interrupt of equal or higher p riority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. if the instruction in progress is not in its final cycle, the additional wait time cannot be more than three cycles, since the lo ngest instructions (mul and div) are only four cycles long. if the instruction in progress is reti or an access to ie or ip, the additional wait time cannot be more than five cycles (a maximum of one more cycle to complete the instruction in progress, plus four cycles to complete the next instruction if the instruction is mul or div). thus, in a single - interrupt system, the response time is always more than three cycles and less than nine cycles. other information reset the reset input is the rst pin, whi ch is the input to a schmitt trigger. a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. the cpu responds by generating an internal reset, with the timing shown in f igure 15. the external reset signal is asynchronous to the internal clock. the rst pin is sampled during state 5 phase 2 of every machine cycle. the port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the rst pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the rst pin. the internal reset algorithm writes 0s to all the sfrs except the port latches, the stack pointer, and sbuf. the port latches are ini tialized to ffh, the stack pointer to 07h, and sbuf is indeterminate. table 11 lists the sfrs and their reset values. then internal ram is not affected by reset. on power - up the ram content is indeterminate. table 11. reset values of the sfr's sfr name re set value pc 0000h acc 00h b 00h psw 00h sp 07h dptr 0000h p0 - p3 ffh ip xx000000b ie 0x000000b tmod 00h tcon 00h t2con 00h th0 00h tl0 00h th1 00h tl1 00h th2 00h tl2 00h rcap2h 00h rcap2l 00h scon 00h sbuf indeterminate pcon 0xxx000 0b add xxxxx000b pwm1 x0000000b pwm2 0xxx0000b
a8351601 series (july, 2002, version 1.0 ) 32 amic technology, inc. power - on reset an automatic reset can be obtained when vcc goes through a 1 0 m f capacitor and gnd through an 8.2k resistor, providing the vcc rise time does not exceed 1 msec and the oscillator start - up time does not exceed 10 msec. this power - on reset circuit is shown in figure 15. the cmos devices do not require the 8.2k pulldow n resistor, although its presence does no harm. when power is turned on, the circuit holds the rst pin high for an amount of time that depends on the value of the capacitor and the rate at which it charges. to ensure a good reset, the rst pin must be high long enough to allow the oscillator time to start - up (normally a few msec) plus two machine cycles. note that the port pins will be in a random state until the oscillator has start and the internal reset algorithm has written 1s to them. with this circuit, reducing vcc quickly to 0 causes the rst pin voltage to momentarily fall below 0v. however, this voltage is internally limited, and will not harm the device. vcc gnd rst vcc 10uf + a8351601 w 8.2k figure 15. power-on reset circuit s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 12 osc. periods addr inst addr inst addr inst addr inst addr inst 11 osc. periods 19 osc. periods sample rst sample rst internal reset signal figure 16. reset timing rst ale psen p0
a8351601 series (july, 2002, version 1.0 ) 33 amic technology, inc. power - saving modes of operation the a8351601 has two power - reducing modes. idle and power - do wn. the input through which backup power is supplied during these operations is vcc. figure 17 shows the internal circuitry which implements these features. in the idle mode (idl = 1), the oscillator continues to run and the interrupt, serial port, and tim er blocks continue to be clocked, but the clock signal is gated off to the cpu. in power - down (pd = 1), the oscillator is frozen. the idle and power - down modes are activated by setting bits in special function register pcon. idle mode an instruction that s ets pcon.0 is the last instruction executed before the idle mode begins. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one fol lowing the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to indicate whether an interrupt occurred during normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag b its. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset must be held active for only two machine cycles (24 oscillator periods) to complete the reset. the signal at the rst pin clears the idl bit directly and asynchronously. at this time, the cpu resumes program execution from where it left off; that is, at the instruction followi ng the one that invoked the idle mode. as shown in figure 16, two or three machine cycles of program execution may take place before the internal reset algorithm takes control. on - chip hardware inhibits access to the internal ram during his time, but acces s to the port pins is not inhibited. to eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes idle should not write to a port pin or to external data ram. power - down mode an instruction that set s pcon.1 is the last instruction executed before power - down mode begins. in the power down mode, the on - chip oscillator stops. with the clock frozen, all functions are stopped, but the on - chip ram and special function registers are held. the port pins outp ut the values held by their respective sfrs. ale and psen output high. in the power - down mode of operation, vcc can be reduced to as low as 2v. however, vcc must not be reduced before the power - down mode is invoked, and vcc must be resto red to its normal operating level before the power - down mode is terminated. the reset that terminates power - down also frees the oscillator. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10 msec). reset redefines all the sfrs but does not change the on - chip ram. osc xtal2 clock gen idl pd cpu interrupt, serial port, timer blocks xtal1 figure 17. idle and power-down hardware
a8351601 series (july, 2002, version 1.0 ) 34 amic technology, inc. xtal 2 xtal 1 gnd n/c external oscillator signal figure 19. external clock drive configuration oscillator characteristics the oscillator connections are shown as figure 18 and figure 19. when exte rnal clock is used, the internal clock will be gotten through a divide - by - two flip - flop. (above table shows the reference values for crystal applications) note:c1,c2,r components refer to figure 18. crystal c1 c2 r 16mhz 20p 20p - 32mhz 5p 5p 3k 40mhz 5p 5p 2k
a8351601 series (july, 2002, version 1.0 ) 35 amic technology, inc. recommended dc operating conditions ( t a = - 10 c to + 70 c, vcc = 5v 10% or vcc = 3v 10% ) symbol parameter min. typ. max. unit vcc supply voltage (vcc= 5v 10%) 4.5 5.0 5.5 v vcc supply voltage (vcc= 3v 10%) 2.7 3.0 3.3 v gnd ground 0 0 0 v v ih* input high voltage 2.4 - vcc+0.2 v v il input low voltage 0 - 0.6 v * xtal1 is a cmos input. reset is a schmitt trigger input. the min. of v ih is 3.5 volts for these two pins. absolute maximum ratings* vcc to gnd . . . . . . . . . . . . . . . . . . . . . ? 0.3v to +7.0v in, in/out volt to gnd . . . . . . . . . - 0.5v to vcc + 0.5v operating temperature, topr . . . . . . . - 25 c to + 85 c storage temperature, tstg . . . . . . . . . - 55 c to + 125 c power dissipation 1* , pr . . . . . . . . . . . . . . . . . . . . . . 1w soldering temperature & time . . . . . . . . . 2 60 c, 10sec 1* : operating frequency is 40mhz(5v 10%) 2* : operating frequency is 16mhz(3v 10%) *comments stresses above those listed under ?absolute maximum ratings? may cause permanent damage to this device. these are stress ratings only. functio nal operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reli ability. dc electrical characteristics (t a = - 10 c to + 70 c, vcc = 5v 10% or vcc = 3v 10%) symbol parameter min. max. unit conditions ? i li input leakage current - 2 m a v in = gnd to vcc ? i lo output leakage current - 2 m a v i/o = gnd to vcc i cc 1 operating current - 50 ma foper = 40mhz(df=0) external oscillator is on xtal1 pin no load (vcc= 5v) i cc2 operating current - 15 ma foper = 16mhz(df=0) external oscillator is on xtal1 pin no load (vcc= 3v) i idle1 idle mode current - 6 ma fidle = 14. 7456mhz(df=0) external oscillator is on xtal1 pin no load (vcc= 5v) i idle2 idle mode current - 3 ma fidle = 14.7456mhz(df=0) external oscillator is on xtal1 pin no load (vcc= 3v)
a8351601 series (july, 2002, version 1.0 ) 36 amic technology, inc. dc electrical characteristics (continued) symbol parameter min. max. u nit conditions i power power down mode current - 4 m a fpower =14.7456mhz(df=0) external oscillator is on xtal1 pin no load (vcc= 5v) i power power down mode current - 2 m a fpower = 14.7456mhz(df=0) external oscillator is on xtal1 pin no load (vcc= 3v) v ol output low voltage (ale, psen , pwm,p0,p1,p2,p3) - 0.45 v i ol = 4ma v oh1 output high voltage (p0, p1, p2, p3) 2.4 - v i oh = - 70 m a (vcc= 5v ) v oh1 output high voltage (p0, p1, p2, p3) 2.4 - v i oh = - 12 m a (vcc= 3 v ) v oh2 1 outpu t high voltage (ale, psen , pwm , p0,p2) 2.4 - v i oh = - 400 m a (vcc= 5 v ) v oh2 1 output high voltage (ale, psen , pwm , p0,p2) 2.4 - v i oh = - 200 m a (vcc= 3 v ) c 1 input pin capacitance - 10 pf 1mh z , 25 c 1. p0, p2, al e and /psen are tested in the external access mode.
a8351601 series (july, 2002, version 1.0 ) 37 amic technology, inc. ac characteristics (t a = - 10 c to + 70 c, vcc = 5v 10% or vcc = 3v 10%) symbol parameter min. max. unit program memory cycle t ap ale pulse width 2t ck ? 20 1 - ns t als address valid to ale low 1t ck - ns t alh address hold from ale low 1t ck - ns t op psen pulse width 3t ck - 20 1 - ns t ao ale low to psen low 1t ck - ns t oi 2 psen low to valid instruction in - 2t ck ns t ido input instruction hold after psen high - 1t ck ns t ifo input instruction float after psen high - 1t ck ns external clock(vcc =5v 10% or vcc = 3v 10%) f oper clock frequency (vcc =5v 10%) 0 40 mh z f oper clock frequency (vcc =3v 10%) 0 16 mh z t ck 3 clock period 25 - ns t ckh 4 clock high time 10 - ns t ckl 4 clock low time 10 - ns data memory cycle t pr rd pulse width 6t ck - 20 1 - ns t pd rd low to valid data in - 4t ck ns t dhr data hold from rd high 0 2t ck ns t dfr data float from rd high 0 2t ck ns t ar ale low to rd low 3t ck 3t ck + 20 1 ns t wp wr pulse width 6t ck - 20 1 - ns t ds valid data to wr low 1t ck - ns t dhw data hold from wr high 1t ck - ns t aw ale low to wr low 3t ck 3t ck + 20 1 ns serial port cycle t sck serial port clock 12t ck - ns t ki clock rising edge to valid input data - 11t ck ns t ikh input data to serial clock rising clock hold time 0 - ns t oks output data to serial clock rising edge setup time 11t ck - ns t okh output data to serial clock rising edge hold time 1t ck - ns 1. this 20 ns is due to buffer driving delay and wire loading. 2. ins truction cycle time is 12 t ck. 3. tck = 1/ f oper 4. there are no duty cycle requirements on the xtal1 input.
a8351601 series (july, 2002, version 1.0 ) 38 amic technology, inc. timing waveforms program memory cycle clock input waveform t ap s1 s2 s3 s4 s5 s6 s1 xtal 1 ale t ao psen port 2 a8 - a15 a8 - a15 t op t als a0 - a7 a0 - a7 port 0 t alh t oi t iho t ifo instruction in instruction in xtal 1 t ckh t ckl t ck
a8351601 series (july, 2002, version 1.0 ) 39 amic technology, inc. timing waveforms (continued) data memory read cycle data memory write cycle se rial port timing ? shift register mode t dhr a0-a7 s4 s5 s6 s1 s2 s3 s4 xtal 1 s5 s6 ale psen port 2 a8-a15 data in a0-a7 port 0 rd t ar t rd t dfr t rp t ds t dhw a0-a7 s4 s5 s6 s1 s2 s3 s4 xtal 1 s5 s6 ale psen port 2 a8-a15 port 0 t wp data out t aw wr 0 1 2 3 4 5 6 7 8 instruction t sck t oks t okh t ki t ikh valid valid valid valid valid valid valid valid 0 1 2 3 4 5 6 7 set ti set ri ale clock output data input data
a8351601 series (july, 2002, version 1.0 ) 40 amic technology, inc. ordering information (vcc=5v 10%) part no. ram freq (mh z ) package a8351601 - 40 256 byte 40 40l p - dip a8351601l - 40 256 byte 40 44l plcc a8351601f - 40 256 byte 40 44l qfp
a8351601 series (july, 2002, version 1.0 ) 41 amic technology, inc. package information p - dip 40l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.210 - - 5.344 a 1 0.015 - - 0.381 - - a 2 0.150 0.155 0.160 3.810 3.937 4.064 b 0.018 typ 0.457 ty p b 1 0.050 typ 1.270 typ c - 0.010 - - 0.254 - d 2.049 2.054 2.059 52.045 52.172 52.299 e 0.590 0.600 0.610 14.986 15.240 15.494 e 1 0.542 0.547 0.552 13.767 13.894 14.021 e 1 0.100 typ 2.540 typ l 0.120 0.130 0.140 3.048 3.302 3.556 e a 0.622 0.642 0 .662 15.799 16.307 16.815 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 1 40 e 1 a 2 a l e e a d c q 0 o/15o 20 21 b 1 b a 1 base plane seating plane e 1
a8351601 series (july, 2002, version 1.0 ) 42 amic technology, inc. package information plcc 44l outline dimension unit: inches/mm dimensions in inches dimensions in mm symbol mi n nom max min nom max a - - 0.185 - - 4.70 d 0.648 0.653 0.658 16.46 16.59 16.71 e 0.648 0.653 0.658 16.46 16.59 16.71 h d 0.680 0.690 0.700 17.27 17.53 17.78 h e 0.680 0.690 0.700 17.27 17.53 17.78 l 0.090 0.100 0.110 2.29 2.54 2.79 q 0 - 10 0 - 10 notes: 1. dimensions d and e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only. h d d 7 17 18 28 29 39 1 6 e h e 44 40 a 1 a 2 a e g d seating plane b 1 b 0.150 ref 0.020 min l 0.630/0.590 0.050 ref 0.022/0.016 0.032/0.026 g e c 0.630/0.590 0.014/0.0008 d 0.004 y
a8351601 series (july, 2002, version 1.0 ) 43 amic technology, inc. package information qfp 44l outline dimensions unit: inches/mm b e a a 2 a 1 d 0.10 see detail a l 1.6 detail a q 12 22 33 23 34 44 1 11 e e 1 d d 1 c 0.25 gauge plane seating plane 0.20 min min 0 dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.106 - - 2.7 a 1 0.010 0.012 0.014 0.25 0.30 0.35 a 2 0.0748 0.0787 0.0866 1.9 2.0 2.2 b 0.012 typ 0.3 typ d 0.5118 0.5196 0.5274 13.00 13.20 13.40 d 1 0.3897 0.3937 0.3977 9.9 10.00 10.10 e 0.5118 0.5196 0.5275 13.00 13.20 13.40 e 1 0.3897 0.3937 0.3977 9.9 10.00 10.10 l 0.0287 0.0346 0.0366 0.73 0.88 0.93 e 0.0315 typ 0.80 typ c 0.0021 0.0060 0.0099 0.1 0.15 0.2 q 0 - 7 0 - 7 notes: 1. dimensions d 1 and e 1 do not include mold protrusion. 2. dimension b does not include dambar protrusion.

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